When displaying an image, a display apparatus needs a shift register (namely a gate electrode driving circuit) to scan pixel units. The shift register includes multiple cascading shift register units, each of which corresponds to a line of pixel units. The multiple cascading shift register units realize line-by-line scan-driving of each line of pixel units in the display apparatus to display the image.
The related art provides a shift register unit, which mainly includes an input circuit, an output circuit, a resetting control circuit and a reset circuit. The input circuit is configured to input an input signal from an input signal end to a first node so as to charge the first node. The output circuit is configured to input a driving signal to an output end under the control of the first node. The resetting control circuit is configured to control the electric potential of a second node under the control of a clock signal end. The reset circuit is configured to reset the first node and the output end under the control of the second node.
However, when both the clock signal and the input signal are in effective electric potentials, both the input circuit and the resetting control circuit may be in a working state as the resetting control circuit is controlled by the clock signal, which may affect the stability of the electric potentials of the first and second nodes.